As MOSFET and CMOS device characteristic sizes are scaled below 0.25 microns including below 0.1 micron, the device designs need to be modified for each generation of device scaling down. For example, short channel effects (SCE) are one of the most important challenges for designers to overcome as device critical dimensions are scaled down. Among the many manifestations of SCE, are Voltage threshold (VT) rolloff, drain induced barrier lowering (DIBL), and subthreshold swing variation.
Source/Drain (S/D) junction depth and channel doping are some of the few parameters that can be changed to reduce SCE. Since the source drain extension (SDE) implants are self-aligned to the gate edge, the junction depth of the S/D regions is typically scaled to the gate length (LG). One problem with reducing junction depth is the effect of increasing the S/D region sheet resistance, which reduces drive current (ID).
One approach to reducing the increase in S/D sheet resistance with shallower junction depths is to form salicides over the S/D regions. However, the width of spacers which mask an underlying lightly doped regions also referred to as source drain extension (SDE) regions during a S/D implant process have the effect of reducing the amount of salicide that may be formed over the S/D and SDE regions. Therefore, while it may be desirable to have a desired spacer width and a desired underlying SDE region width, the spacer width limits the degree of lowering the sheet resistance of the S/D region by salicide formation leading to lower drive current (ID).
In addition, as gate lengths become smaller, for example less than about 80 nanometers, conventional processes for forming spacers are no longer adequate to precisely position the S/D implant regions, thereby leading to increased SCE. In some approaches in the prior art, disposable spacers have been proposed to address the problem of having a desirable spacer width to form a desired S/D region and subsequent salicide width to lower S/D region sheet resistance. Among the shortcomings of disposable spacers includes costly and complicated processes requiring extra process steps which undesirably decreases throughput and adds to cost. In addition, disposable spacers lead to reduced control in forming a selected level of tensile or compressive stresses in the channel region to achieve improved charge mobility.
There is therefore a need in the semiconductor integrated circuit manufacturing art for an improved method for forming dielectric spacers to achieve desired dimensions while reducing S/D region electrical resistance and associated SCE effects while increasing charge mobility at acceptable process throughput and process cost.
It is therefore among the objects of the present invention to provide an improved method for forming dielectric spacers to achieve desired dimensions while reducing S/D region electrical resistance and associated SCE effects while increasing charge mobility at acceptable process throughput and process cost, as well as overcoming other shortcomings of the prior art.
In another approach, strain in the channel is introduced after the transistor is formed. In this approach, a high stress film is formed over a completed transistor structure formed in a silicon substrate. The high stress film or stressor exerts significant influence on the channel, modifying the silicon lattice spacing in the channel region, and thus introducing strain in the channel region. In this case, the stressor is placed above the completed transistor structure. This scheme is described in detail in a paper by A. Shimizu et al., entitled “Local mechanical stress control (LMC): a new technique for CMOS performance enhancement,” published in pp. 433–436 of the Digest of Technical Papers of the 2001 International Electron Device Meeting, which is incorporated herein by reference.